The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2023

Filed:

Aug. 23, 2021
Applicant:

Yazaki Corporation, Tokyo, JP;

Inventors:

Mitsuaki Morimoto, Shizuoka, JP;

Kazuo Sugimura, Shizuoka, JP;

Kazuya Tsubaki, Shizuoka, JP;

Eiichiro Oishi, Shizuoka, JP;

Yasuyuki Shigezane, Shizuoka, JP;

Assignee:

YAZAKI CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/07 (2006.01); H01L 23/50 (2006.01);
U.S. Cl.
CPC ...
H01L 25/072 (2013.01); H01L 23/50 (2013.01);
Abstract

In a semiconductor module, semiconductor chips are each provided with a drain portion on one of a pair of surfaces facing each other, and a source portion and a gate portion on the other surface. Substrates each include three power supply patterns capable of transmitting power supplied from a power supply, and at least two signal patterns capable of transmitting a control signal. The three power supply patterns and the two signal patterns extend in parallel to each other along a first direction. Among the three power supply patterns, two of them are capable of mounting the semiconductor chips and connectable to the drain portions of the mounted semiconductor chips, and remaining one of them is connectable to the source portions of the semiconductor chips. The two signal patterns are connectable to the gate portions of the semiconductor chips.


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