The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2023

Filed:

Dec. 07, 2020
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Hiromitsu Harashima, Yokohama, JP;

Yasushi Kameda, Hayama, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H01L 23/544 (2006.01); H01L 21/66 (2006.01); H01L 21/78 (2006.01); G01R 31/28 (2006.01); H01L 27/11582 (2017.01); H01L 27/11565 (2017.01);
U.S. Cl.
CPC ...
H01L 22/34 (2013.01); G01R 31/2884 (2013.01); H01L 21/78 (2013.01); H01L 27/11582 (2013.01); H01L 27/11565 (2013.01);
Abstract

A semiconductor wafer according to the present embodiment is a semiconductor wafer having a first face. A plurality of chip structures are provided on a plurality of chip regions of the first face. A test structure is provided on dicing regions between adjacent ones of the chip regions. The chip structures each comprise first integrated circuits provided on the semiconductor wafer, and a first stacked body provided above the first integrated circuits and including a plurality of first layers and a plurality of second layers different from the first layers alternately stacked. The test structure comprises second integrated circuits provided on the semiconductor wafer, and a second stacked body provided above the second integrated circuits and including the first layers and the second layers alternately stacked.


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