The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2023

Filed:

Mar. 26, 2020
Applicant:

Beijing Boe Technology Development Co., Ltd., Beijing, CN;

Inventors:

Ronghua Lan, Beijing, CN;

Junrui Zhang, Beijing, CN;

Xuehui Zhu, Beijing, CN;

Zhidong Wang, Beijing, CN;

Lijia Zhou, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01); G11C 7/10 (2006.01); G09G 3/20 (2006.01); G11C 8/06 (2006.01); G11C 8/10 (2006.01); G09G 3/3266 (2016.01); G11C 19/28 (2006.01); G11C 8/18 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1096 (2013.01); G09G 3/20 (2013.01); G09G 3/3266 (2013.01); G09G 3/3677 (2013.01); G09G 3/3688 (2013.01); G11C 7/1087 (2013.01); G11C 8/06 (2013.01); G11C 8/10 (2013.01); G09G 2310/02 (2013.01); G09G 2310/0286 (2013.01); G11C 8/18 (2013.01); G11C 19/28 (2013.01);
Abstract

An address latch, a display device, and an address latching method are disclosed. The address latch includes a write control circuit, a write latch circuit, a latch control circuit, an intermediate latch circuit, and an output latch circuit. The write latch circuit is configured to latch an address data in response to N write control signals generated by the write control circuit, N data bits of the address data are divided into (M−1) data bit groups; the latch control circuit is configured to sequentially generate M latch control signals; the intermediate latch circuit is configured to, in response to first to (M−1)-th latch control signals, latch first to (M−1)-th data bit groups latched by the write latch circuit in a time-division manner; and the output latch circuit is configured to output the address data latched by the intermediate latch circuit in response to an M-th latch control signal.


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