The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2023

Filed:

Aug. 31, 2021
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Goichi Ootomo, Kawasaki Kanagawa, JP;

Tomoaki Suzuki, Chigasaki Kanagawa, JP;

Assignee:

KIOXIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/42 (2006.01); G06F 13/16 (2006.01); G11C 16/32 (2006.01); G06F 13/40 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1689 (2013.01); G06F 13/4027 (2013.01); G06F 13/4291 (2013.01); G11C 16/32 (2013.01); G11C 16/0483 (2013.01);
Abstract

A semiconductor storage device includes a bridge chip and memory chips connected to the bridge chip by a plurality of channels. The bridge chip includes a first delay circuit for setting the start of a first timing signal for a first memory chip output via a first channel and a second delay circuit for setting the start of for second timing signal for a second memory chip output via a second channel. A controller on the bridge chip controls at least one of the first and second delay circuits to adjust the start time of at least one of the first and second timing signals such that data sequences from the first and second memory chips will be aligned in time. The controller combines the data sequence from the first memory chip with the data sequence from the second memory chip to generate an interleaved serial sequence.


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