The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2023

Filed:

Dec. 04, 2020
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Yuki Hayakawa, Tokyo, JP;

Toshiyuki Kaya, Tokyo, JP;

Shinichi Shibahara, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/16 (2006.01); G06F 12/06 (2006.01); G06F 12/084 (2016.01); G06F 12/0842 (2016.01); G06F 12/0815 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0815 (2013.01); G06F 11/16 (2013.01); G06F 11/167 (2013.01); G06F 11/1666 (2013.01); G06F 11/1675 (2013.01); G06F 12/063 (2013.01); G06F 12/084 (2013.01); G06F 12/0842 (2013.01);
Abstract

A semiconductor device includes first and second CPUs, first and second SPUs for controlling a snoop operation, a controller supporting ASIL D of a functional safety standard and a memory. The controller sets permission of the snoop operation to the first and second SPUs when a software lock-step is not performed. The controller sets prohibition of the snoop operation to the first and second SPUs when the software lock-step is performed. The first CPU executes a first software for the software lock-step, and writes an execution result in a first area for the memory. The second CPU executes a second software for the software lock-step, and writes an execution result in a second area of the memory. The execution result written in the first area is compared with the execution result written in the second area.


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