The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 03, 2023
Filed:
Jul. 20, 2018
Applicant:
Sony Semiconductor Solutions Corporation, Kanagawa, JP;
Inventors:
Hiroo Takahashi, Kanagawa, JP;
Naohiro Koshisaka, Kanagawa, JP;
Assignee:
Sony Semiconductor Solutions Corporation, Kanagawa, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/07 (2006.01); G06F 13/42 (2006.01); H04L 1/00 (2006.01); H04L 5/00 (2006.01); H04N 5/232 (2006.01);
U.S. Cl.
CPC ...
G06F 11/0772 (2013.01); G06F 11/0742 (2013.01); G06F 11/0751 (2013.01); G06F 11/0793 (2013.01); G06F 13/4282 (2013.01); H04L 1/0061 (2013.01); H04L 5/0055 (2013.01); G06F 2213/0016 (2013.01); H04N 5/23203 (2013.01);
Abstract
A CCI (I3C SDR) processing section determines status of an index when requested to be accessed by an I3C master for a read operation. An error handling section then controls an I3C slaveto detect occurrence of an error based on the status of the index and to neglect all communication until communication is restarted or stopped by the I3C master, the I3C slavebeing further controlled to send a NACK response when performing acknowledge processing on a signal sent from the I3C master. This technology can be applied to the I3C bus, for example.