The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2023

Filed:

Mar. 16, 2021
Applicant:

Coherent Logix, Incorporated, Austin, TX (US);

Inventors:

Michael B. Doerr, Hampton Falls, NH (US);

Carl S. Dobbs, Austin, TX (US);

Michael B. Solka, Austin, TX (US);

Michael R. Trocino, Austin, TX (US);

Kenneth R. Faulkner, Austin, TX (US);

Keith M. Bindloss, Irvine, CA (US);

Sumeer Arya, Austin, TX (US);

John Mark Beardslee, Menlo Park, CA (US);

David A. Gibson, Austin, TX (US);

Assignee:

Coherent Logix, Inc., Austin, TX (US);

Attorney:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 9/30 (2018.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3895 (2013.01); G06F 9/3005 (2013.01); G06F 9/30083 (2013.01); G06F 9/30145 (2013.01); G06F 9/30181 (2013.01); G06F 9/3802 (2013.01); G06F 9/3826 (2013.01); G06F 9/3853 (2013.01); G06F 9/3867 (2013.01); G06F 9/3885 (2013.01); G06F 12/0215 (2013.01); G06F 9/3851 (2013.01);
Abstract

Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. First and second address generator units may generate, based on different fields of the multi-part instruction, addresses from which to retrieve first and second data for use by an execution unit for the multi-part instruction or a subsequent multi-part instruction. The execution units may perform operations using a single pipeline or multiple pipelines based on third and fourth fields of the multi-part instruction.


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