The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2022

Filed:

Jul. 22, 2021
Applicant:

Analog Devices International Unlimited Company, Limerick, IE;

Inventors:

Mohamed A. Shehata, Dublin, IE;

James Breslin, Ennis, IE;

Michael F. Keaveney, lisnagry, IE;

Hyman Shanan, Franklin Park, NJ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03B 5/18 (2006.01); H03K 5/00 (2006.01); G04F 10/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/00006 (2013.01); G04F 10/005 (2013.01); H03B 5/1841 (2013.01); H03B 2200/0016 (2013.01); H03B 2201/0208 (2013.01);
Abstract

Rotary traveling wave oscillator-based (RTWO-based) frequency multipliers are provided herein. In certain embodiments, an RTWO-based frequency multiplier includes an RTWO that generates a plurality of clock signal phases of a first frequency, and an edge combiner that processes the clock signal phases to generate an output clock signal having a second frequency that is a multiple of the first frequency. The edge combiner can be implemented as a logic-based combining circuit that combines the clock signal phases from the RTWO. For example, the edge combiner can include parallel stacks of transistors operating on different clock signal phases, with the stacks selectively activating based on timing of the clock signal phases to generate the output clock signal of multiplied frequency.


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