The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2022

Filed:

Jan. 12, 2021
Applicants:

Sanken Electric Co., Ltd., Niiza, JP;

Allegro Microsystems, Llc, Manchester, NH (US);

Inventor:

Taro Kondo, Niiza, JP;

Assignees:

SANKEN ELECTRIC CO., LTD., Niiza, JP;

Allegro MicroSystems, LLC, Manchester, NH (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7811 (2013.01); H01L 29/1095 (2013.01); H01L 29/404 (2013.01); H01L 29/407 (2013.01); H01L 29/7813 (2013.01);
Abstract

A semiconductor device is disclosed that includes a group of trenches positioned in active region inside a first semiconductor region. A first trench is positioned in an outer peripheral region on an outer side of an active region. A second trench is positioned on an outer side of the first trench positioned in the outer peripheral region on the outer side of the active region. A mesa portion is positioned between the first and the second trenches. An insulating layer is positioned inside the first and second trenches. A second field plate is positioned inside the insulating layer in the first trench. A third field plate positioned inside the second insulating layer in the second trench. The mesa portion includes the semiconductor region electrically coupled to the first main electrode on an outermost side. The first trench does not have the gate electrode at upper part of the first trench.


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