The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2022

Filed:

Sep. 28, 2020
Applicants:

Wuhan Tianma Micro-electronics Co., Ltd., Wuhan, CN;

Wuhan Tianma Microelectronics Co., Ltd. Shanghai Branch, Shanghai, CN;

Inventors:

Zi Xu, Shanghai, CN;

Xinzhao Liu, Shanghai, CN;

Liujing Fan, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/32 (2006.01); H01L 51/52 (2006.01); H01L 51/50 (2006.01); H01L 51/56 (2006.01);
U.S. Cl.
CPC ...
H01L 27/3276 (2013.01); H01L 27/323 (2013.01); H01L 51/5056 (2013.01); H01L 51/5072 (2013.01); H01L 51/5092 (2013.01); H01L 51/5237 (2013.01); H01L 51/5284 (2013.01); H01L 51/5293 (2013.01); H01L 51/56 (2013.01); H01L 2227/323 (2013.01);
Abstract

A display panel, a method for fabrication a display panel, and a display device are provided. The display panel includes a display area, and a non-display area surrounding the display area and a first bezel area being in the non-display area; a substrate; a wiring layer, disposed on the substrate and in the non-display area, and including at least one first lead and at least one second lead, and at least a partial line segment of the at least one first lead and at least a partial line segment of the at least one second lead are disposed in the first bezel area; a polarizer disposed on a side of the wiring layer away from the substrate; and a first light-emitting layer, at least distributed in the first bezel area and, along a direction perpendicular to the substrate, disposed between the substrate and the wiring layer.


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