The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2022

Filed:

Aug. 11, 2021
Applicant:

Mediatek Singapore Pte. Ltd., Singapore, SG;

Inventors:

Zhigang Duan, Singapore, SG;

Jinghao Chen, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 25/065 (2006.01); H01L 23/522 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/5222 (2013.01); H01L 28/60 (2013.01);
Abstract

A semiconductor structure includes a first substrate, a first semiconductor die, a second semiconductor die, and a multi-terminal multi-capacitor structure. The first substrate includes a wiring structure. The first semiconductor die and the second semiconductor die are disposed on the first substrate. The multi-terminal multi-capacitor structure is disposed on the first substrate and includes a second substrate, an insulating layer, a first multi-terminal capacitor, and a second multi-terminal capacitor. The insulating layer is disposed over the second substrate. The first multi-terminal capacitor is disposed over the insulating layer and electrically coupled to the first semiconductor die through the wiring structure. The second multi-terminal capacitor is disposed over the insulating layer and electrically coupled to the second semiconductor die through the wiring structure, wherein the first multi-terminal capacitor and the second multi-terminal capacitor are electrically isolated from the second substrate.


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