The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2022

Filed:

Oct. 09, 2020
Applicants:

Srinivas Katkoori, Wesley Chapel, FL (US);

Rohith Prasad Challa, Dayton, NJ (US);

Sheikh Ariful Islam, Tampa, FL (US);

Inventors:

Srinivas Katkoori, Wesley Chapel, FL (US);

Rohith Prasad Challa, Dayton, NJ (US);

Sheikh Ariful Islam, Tampa, FL (US);

Assignee:

University of South Florida, Tampa, FL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/75 (2013.01); H03K 19/20 (2006.01); H03K 3/037 (2006.01);
U.S. Cl.
CPC ...
G06F 21/75 (2013.01); H03K 3/0375 (2013.01); H03K 19/20 (2013.01);
Abstract

The present disclosure presents various systems and methods for implementing a physical unclonable function device. One such method comprises providing an integrated circuit having a plurality of set/reset flip flop logic circuits, wherein each of the set/reset flip flop logic circuits enters a metastable state for a particular input sequence. The method includes varying circuit parameters for each of the plurality of set/reset flip flop logic circuits to account for manufacturing variations in the set/reset flip flop logic circuits and enable generating a stable but random output in response to the particular input sequence. Thus, by applying the particular input sequence to the integrated circuit, a unique identifier for the integrated circuit can be derived from an output response of the plurality of set/reset flip flop logic circuits.


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