The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2022

Filed:

Feb. 22, 2021
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Israel Zimmerman, Ashdod, IL;

Mahmud Asfur, Bat-Yam, IL;

Mordekhay Zehavi, Raanana, IL;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 15/80 (2006.01); H03M 13/11 (2006.01); G06F 16/23 (2019.01); G06F 11/10 (2006.01);
U.S. Cl.
CPC ...
G06F 13/161 (2013.01); G06F 11/1004 (2013.01); G06F 13/1668 (2013.01); G06F 15/80 (2013.01); G06F 16/2379 (2019.01); H03M 13/1102 (2013.01);
Abstract

A method and apparatus for the increase of internal data throughput and processing capability for SSD's, to enable processing of database commands on an SSD. A front-end ASIC is provided with 256 to 512 RISC processing cores to enable decomposition and parallelization of host commands to front-end module (FM) ASICs that each in turn are coupled to multiple NVM dies, as well as processing of host database operations such as insert, select, update, and delete. Each FM ASIC is architected to increase parity bits to 33.3% of NVM data, and process parity data with 14 LDPC's. By increasing the parity bits to 33.3%, BER is reduced, power consumption is reduced, and data throughput within the SSD is increased.


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