The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2022

Filed:

Oct. 12, 2020
Applicant:

Infineon Technolgies Llc, San Jose, CA (US);

Inventors:

Stephan Rosner, Campbell, CA (US);

Sergey Ostrikov, Redwood City, CA (US);

Clifford Zitlaw, San Jose, CA (US);

Yuichi Ise, Kanagawa, JP;

Assignee:

Infineon Technologies LLC, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/10 (2016.01); G06F 21/57 (2013.01); G06F 9/24 (2006.01); G06F 8/654 (2018.01); G06F 11/10 (2006.01); G06F 8/71 (2018.01); G06F 8/60 (2018.01); G06F 12/02 (2006.01); G06F 8/65 (2018.01); G06F 9/50 (2006.01); G06F 12/14 (2006.01); G06F 9/32 (2018.01); G06F 9/445 (2018.01); G06F 9/4401 (2018.01); G06F 9/26 (2006.01);
U.S. Cl.
CPC ...
G06F 8/654 (2018.02); G06F 12/10 (2013.01); G06F 8/60 (2013.01); G06F 8/65 (2013.01); G06F 8/71 (2013.01); G06F 9/268 (2013.01); G06F 9/328 (2013.01); G06F 9/4401 (2013.01); G06F 9/4403 (2013.01); G06F 9/44521 (2013.01); G06F 9/5061 (2013.01); G06F 11/1068 (2013.01); G06F 12/0246 (2013.01); G06F 12/0284 (2013.01); G06F 12/1433 (2013.01); G06F 2212/1008 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/657 (2013.01);
Abstract

A method can include storing first instruction data in a first region of a nonvolatile memory device; mapping addresses of the first region to predetermined memory address spaces of a processor device; executing the first instruction data from the first region with the processor device; receiving second instruction data for the processor device. While the first instruction data remains available to the processor device, the second instruction data can be written into a second region of the nonvolatile memory device. By operation of the processor device, addresses of the second region can be remapped to the predetermined memory address spaces of the processor device; and executing the second instruction data from the second region with the processor device.


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