The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2022

Filed:

Mar. 19, 2021
Applicant:

Hrl Laboratories, Llc, Malibu, CA (US);

Inventors:

Florian G. Herrault, Malibu, CA (US);

Jonathan J. Lynch, Malibu, CA (US);

Assignee:

HRL LABORATORIES, LLC, Malibu, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 23/482 (2006.01); H01L 23/367 (2006.01); H01L 25/065 (2006.01); H01L 25/16 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); G01S 7/03 (2006.01); H01Q 1/32 (2006.01); H01Q 23/00 (2006.01);
U.S. Cl.
CPC ...
G01S 7/032 (2013.01); H01Q 1/3233 (2013.01); H01Q 23/00 (2013.01);
Abstract

An integrated radar circuit comprising: a first substrate, of a first semiconductor material, said first substrate comprising an integrated transmit and receive radar circuit; a second substrate, of a second semiconductor material, said second substrate comprising at least on through-substrate cavity having cavity walls; at least one discrete transistor chip, of a third semiconductor material, said at least one discrete transistor chip having chip walls and being held in said at least one through-substrate cavity by a metal filling extending from at least one cavity wall to at least one chip wall; a conductor on said second substrate, electrically connecting a portion of said integrated transmit and receive radar circuit to a discrete transistor on said at least one discrete transistor chip.


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