The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2022

Filed:

Oct. 08, 2020
Applicant:

Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;

Inventors:

James Wells, Edinburgh, GB;

Saurabh Singh, Edinburgh, GB;

Huy Binh Le, Edinburgh, GB;

Gavin Wilson, Edinburgh, GB;

Niall McGurnaghan, Edinburgh, GB;

Simon R. Foster, Reading, GB;

Mark McCloy-Stevens, Edinburgh, GB;

Assignee:

Cirrus Logic, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G01R 31/56 (2020.01);
U.S. Cl.
CPC ...
G01R 31/2884 (2013.01); G01R 31/56 (2020.01);
Abstract

The present disclosure relates to self-test circuitry for a system that includes one or more current control subsystems, each current control subsystem having a load terminal for coupling the current control subsystem to a load. The self-test circuitry comprises: a signal path associated with each current control subsystem, each signal path configured to selectively couple a measurement node to the load terminal of the current control subsystem, wherein the measurement node is common to all of the signal paths; voltage detection circuitry; and test voltage source circuitry configured to provide a test voltage to the measurement node. The voltage detection circuitry is operable to output a signal indicative of a fault condition if a voltage detected at the measurement node differs from the test voltage when the measurement node is coupled to the load terminal.


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