The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 20, 2022

Filed:

Nov. 19, 2019
Applicant:

Canon Kabushiki Kaisha, Tokyo, JP;

Inventors:

Tatsunori Kato, Kawasaki, JP;

Akira Oseto, Kawasaki, JP;

Ryunosuke Ishii, Tokyo, JP;

Takanori Watanabe, Yamato, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H01L 27/11 (2006.01); H01L 23/528 (2006.01); G11C 11/418 (2006.01); H01L 23/00 (2006.01); G11C 11/419 (2006.01); H04N 5/378 (2011.01); H04N 5/376 (2011.01); H04N 5/369 (2011.01);
U.S. Cl.
CPC ...
H01L 27/14634 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01); H01L 23/528 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 27/1104 (2013.01); H01L 27/1116 (2013.01); H04N 5/376 (2013.01); H04N 5/378 (2013.01); H04N 5/379 (2018.08); H01L 2224/05647 (2013.01); H01L 2224/08147 (2013.01); H01L 2924/1437 (2013.01);
Abstract

A photoelectric conversion device including a plurality of substrates in a stacked state, the plurality of substrates including a first substrate and a second substrate electrically connected to each other, the photoelectric conversion device comprising: a memory cell unit including row-selection lines that are to be driven upon selection of a row of a memory cell array and column-selection lines that are to be driven upon selection of a column of the memory cell array; and a memory peripheral circuit unit that includes row-selection line connection portions and column-selection line connection portions so as to drive the row-selection lines and to drive the column-selection lines, wherein a first portion that is at least a part of the memory peripheral circuit unit is formed on the first substrate and the memory cell unit is formed on the second substrate.


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