The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 20, 2022

Filed:

Sep. 29, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Sangsoo Lee, Seongnam-si, KR;

Chaeho Kim, Seoul, KR;

Woosung Lee, Yongin-si, KR;

Phil Ouk Nam, Suwon-si, KR;

Junggeun Jee, Siheung-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/11519 (2017.01); H01L 27/11556 (2017.01); H01L 23/535 (2006.01); H01L 27/11565 (2017.01); H01L 27/11573 (2017.01); H01L 27/11529 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 23/535 (2013.01); H01L 27/11519 (2013.01); H01L 27/11529 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11573 (2013.01);
Abstract

Disclosed is a three-dimensional semiconductor memory device including a carbon-containing layer on a substrate, a plurality of electrode interlayer dielectric layers and a plurality of electrode layers that are alternately stacked on the carbon-containing layer, a cell vertical pattern that penetrates at least some of the electrode interlayer dielectric layers and the electrode layers, and a semiconductor pattern between the cell vertical pattern and the carbon-containing layer. The substrate includes a plurality of first grains. The semiconductor pattern includes a plurality of second grains. An average size of the second grains is less than an average size of the first grains.


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