The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 20, 2022

Filed:

Nov. 11, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Kyungin Choi, Seoul, KR;

Dahye Kim, Yongin-si, KR;

Jaemun Kim, Seoul, KR;

Jinbum Kim, Seoul, KR;

Seunghun Lee, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 29/165 (2006.01); H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 21/306 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/02598 (2013.01); H01L 21/02667 (2013.01); H01L 21/30604 (2013.01); H01L 21/76224 (2013.01); H01L 21/823431 (2013.01); H01L 21/823487 (2013.01); H01L 29/0673 (2013.01); H01L 29/165 (2013.01); H01L 29/66545 (2013.01);
Abstract

Integrated circuit devices may include a fin-type active area, a semiconductor liner contacting a side wall of the fin-type active area and including a protrusion portion protruding outward from the fin-type active area in the vicinity of an edge of an upper surface of the fin-type active area, and an isolation layer spaced apart from the fin-type active area with the semiconductor liner therebetween. To manufacture the integrated circuit devices, a crystalline semiconductor layer covering the fin-type active area with a first thickness and an amorphous semiconductor layer covering the mask pattern with a second thickness may be formed, an extended crystalline semiconductor layer covering the mask pattern may be formed by crystalizing the amorphous semiconductor layer, and a semiconductor liner including a protrusion portion may be formed from the extended crystalline semiconductor layer and the crystalline semiconductor layer.


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