The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 20, 2022

Filed:

Mar. 11, 2021
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventor:

Woo Hyun Paik, Gyeonggi-do, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01); G11C 29/44 (2006.01); G11C 29/42 (2006.01); G11C 29/20 (2006.01); G11C 11/406 (2006.01); G11C 29/00 (2006.01); G11C 29/10 (2006.01);
U.S. Cl.
CPC ...
G11C 29/44 (2013.01); G11C 11/40615 (2013.01); G11C 11/40622 (2013.01); G11C 29/10 (2013.01); G11C 29/20 (2013.01); G11C 29/42 (2013.01); G11C 29/76 (2013.01);
Abstract

A memory device includes a latch circuit suitable for storing an input address as a first latch address in response to a first latch signal, and storing an address, selected between the input address and the first latch address, as a second latch address in response to a second latch signal, a test determining circuit suitable for determining whether a memory cell fail occurs, based on test data, and generating a detection signal corresponding to the determination result, in response to a test mode signal, and a control signal generation circuit suitable for comparing the input address to the first and second latch addresses in response to the detection signal, and selectively enabling the first and second latch signals according to the comparison result.


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