The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 20, 2022

Filed:

Mar. 15, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jiwoon Park, Suwon-si, KR;

Jaehyurk Choi, Jeonju-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/32 (2006.01); G06F 3/06 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); H03L 7/081 (2006.01); H03L 7/089 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
G11C 16/32 (2013.01); G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); H03L 7/0812 (2013.01); H03L 7/0891 (2013.01); H01L 25/0657 (2013.01);
Abstract

A storage device includes a semiconductor memory device and a storage controller. The semiconductor memory device receives write data based on a data strobe signal and data signals, and outputs read data based on the data strobe signal and the data signals. The storage controller transmits the data strobe signal and the data signals in parallel to the semiconductor memory device through signal lines. The storage controller includes a first delay circuit that delays the data signals such that some edges of windows of the data signals on the signal lines are desynchronized by first skew offsets which are different from one another.


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