The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 20, 2022

Filed:

Jan. 17, 2019
Applicant:

Tzero Ip, Llc, Salt Lake City, UT (US);

Inventors:

Joel Weight, Sandy, UT (US);

Tron Black, Sandy, UT (US);

Denny Becker, Salt Lake City, UT (US);

Assignee:

tZERO IP, LLC, Salt Lake City, UT (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06Q 20/38 (2012.01); H04L 9/08 (2006.01); H04L 9/30 (2006.01); H04L 9/14 (2006.01); G06Q 20/36 (2012.01); G06Q 20/40 (2012.01); H04L 9/32 (2006.01); G06Q 20/08 (2012.01); H04L 9/06 (2006.01); H04L 9/00 (2022.01);
U.S. Cl.
CPC ...
G06Q 20/3829 (2013.01); G06Q 20/0855 (2013.01); G06Q 20/3672 (2013.01); G06Q 20/3674 (2013.01); G06Q 20/381 (2013.01); G06Q 20/389 (2013.01); G06Q 20/3823 (2013.01); G06Q 20/3827 (2013.01); G06Q 20/40145 (2013.01); H04L 9/0637 (2013.01); H04L 9/0643 (2013.01); H04L 9/085 (2013.01); H04L 9/0819 (2013.01); H04L 9/0894 (2013.01); H04L 9/14 (2013.01); H04L 9/30 (2013.01); H04L 9/321 (2013.01); H04L 9/3231 (2013.01); H04L 9/3239 (2013.01); H04L 9/3247 (2013.01); H04L 9/3297 (2013.01); G06Q 2220/00 (2013.01); H04L 9/50 (2022.05); H04L 2209/56 (2013.01);
Abstract

A computing system that includes at least one processor and at least one memory communicatively coupled to the at least one processor is disclosed. The computing system also includes at least one network interface communicatively coupled to the at least one processor and configured to communicate with at least one vault system, each of the at least one vault system storing a respective one of N private keys or key components associated with a customer. The at least one processor is configured to generate, at the customer device, a sweeping transaction that transfers all funds from at least one input transaction address in a customer wallet to a new transaction address. The at least one processor is also configured to sign the sweeping transaction using at least M of N private keys or key components.


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