The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 20, 2022

Filed:

Nov. 25, 2020
Applicant:

American Megatrends International, Llc, Duluth, GA (US);

Inventors:

Stefano Righi, Lawrenceville, GA (US);

Umasankar Mondal, Snellville, GA (US);

Sanjoy Kumar Maity, Snellville, GA (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 21/57 (2013.01); G06F 21/74 (2013.01); G06F 21/85 (2013.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 21/572 (2013.01); G06F 9/30 (2013.01); G06F 21/74 (2013.01); G06F 21/85 (2013.01); G06F 2221/033 (2013.01);
Abstract

Technologies are described herein for providing a Baseboard Management Controller ('BMC') -based security processor. The disclosed BMC-based security processor can provide a hardware Root of Trust ('RoT') for a computing platform without the addition of specialized silicon to the platform and while minimizing the number of attack points. The disclosed BMC-based security processor can also provide functionality for securely filtering requests made on certain buses in a computing platform. Through implementations of the features identified briefly above, and others described herein, various technical benefits can be achieved such as, but not limited to, increased security as compared to previous computing systems that utilize a BMC to provide a hardware RoT and reduced complexity and cost as compared to previous computing systems that utilize a separate hardware device, such as a Field Programmable Gate Array (“FPGA”) or a microcontroller, to provide a hardware RoT.


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