Throttling access to high latency hybrid memory dimms

Abstract

A throttling engine throttles access to a high latency hybrid memory. A request is received for partition mapping of a virtual address for an R/W memory page. An entry is added to a partition page table that maps a virtual address to a physical address and comprises access information that is R/W. A throttled flag is set in an entry of a partition page extension table. The throttle entry corresponds to the entry. The access information is saved in an original access part of the partition page extension table, and the access information is replaced with an R value. Upon application fault receipt, a throttling test is performed on an address of the application fault. If the throttling test is false, the fault is passed through to an operating system fault handler and the throttling fault stage is ended, otherwise, a delay is implemented for slowing access to the memory.