The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 2022

Filed:

Jun. 20, 2018
Applicant:

Oxford University Innovation Limited, Oxford, GB;

Inventors:

Henry James Snaith, Oxford, GB;

Edward James William Crossland, Oxford, GB;

Andrew Hey, Oxford, GB;

James Ball, Oxford, GB;

Michael Lee, Oxford, GB;

Pablo Docampo, Oxford, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/036 (2006.01); C23C 14/06 (2006.01); H01L 51/42 (2006.01); H01L 31/0224 (2006.01); H01L 31/0352 (2006.01); H01L 31/0725 (2012.01); H01L 31/18 (2006.01); H01L 51/00 (2006.01);
U.S. Cl.
CPC ...
H01L 31/036 (2013.01); C23C 14/06 (2013.01); H01L 31/022466 (2013.01); H01L 31/035272 (2013.01); H01L 31/0725 (2013.01); H01L 31/1864 (2013.01); H01L 31/1884 (2013.01); H01L 51/0032 (2013.01); H01L 51/422 (2013.01); H01L 51/4226 (2013.01); H01L 51/0026 (2013.01); H01L 51/0037 (2013.01); Y02E 10/549 (2013.01);
Abstract

The invention provides an optoelectronic device comprising a photoactive region, which photoactive region comprises: an n-type region comprising at least one n-type layer; a p-type region comprising at least one p-type layer; and, disposed between the n-type region and the p-type region: a layer of a perovskite semiconductor without open porosity. The perovskite semiconductor is generally light-absorbing. In some embodiments, disposed between the n-type region and the p-type region is: (i) a first layer which comprises a scaffold material, which is typically porous, and a perovskite semiconductor, which is typically disposed in pores of the scaffold material; and (ii) a capping layer disposed on said first layer, which capping layer is said layer of a perovskite semiconductor without open porosity, wherein the perovskite semiconductor in the capping layer is in contact with the perovskite semiconductor in the first layer. The layer of the perovskite semiconductor without open porosity (which may be said capping layer) typically forms a planar heterojunction with the n-type region or the p-type region. The invention also provides processes for producing such optoelectronic devices which typically involve solution deposition or vapour deposition of the perovskite. In one embodiment, the process is a low temperature process; for instance, the entire process may be performed at a temperature or temperatures not exceeding 150° C.


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