The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 2022

Filed:

Jan. 26, 2021
Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Shin-Hyuk Yang, Seongnam-si, KR;

Kwang-Soo Lee, Gwangmyeong-si, KR;

Doo-Hyun Kim, Goyang-si, KR;

Jee-Hoon Kim, Cheonan-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/477 (2006.01); H01L 21/469 (2006.01); H01L 21/28 (2006.01); H01L 21/77 (2017.01); H01L 27/32 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 27/3262 (2013.01); H01L 21/469 (2013.01); H01L 21/477 (2013.01); H01L 27/1225 (2013.01); H01L 27/1248 (2013.01); H01L 27/1255 (2013.01); H01L 27/3248 (2013.01); H01L 27/3265 (2013.01); H01L 29/40111 (2019.08); H01L 29/7869 (2013.01); H01L 2021/775 (2013.01); H01L 2227/323 (2013.01);
Abstract

An organic light emitting display device includes a substrate, a buffer layer, an active layer, a gate insulation layer, a protective insulating layer, a gate electrode, an insulating interlayer, source and drain electrodes, and a sub-pixel structure. The buffer layer is disposed on the substrate. The active layer is disposed on the buffer layer, and has a source region, a drain region, and a channel region. The gate insulation layer is disposed in the channel region on the active layer. The protective insulating layer is disposed on the buffer layer, the source and drain regions of the active layer, and the gate insulation layer. The gate electrode is disposed in the channel region on the protective insulating layer. The insulating interlayer is disposed on the gate electrode. The source and drain electrodes are disposed on the insulating interlayer.


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