The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 2022

Filed:

Mar. 22, 2021
Applicant:

Palo Alto Research Center Incorporated, Palo Alto, CA (US);

Inventors:

Christopher L. Chua, San Jose, CA (US);

Qian Wang, Mountain View, CA (US);

Eugene M. Chow, Palo Alto, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 23/532 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01); H01L 23/482 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/566 (2013.01); H01L 23/29 (2013.01); H01L 23/3171 (2013.01); H01L 23/3192 (2013.01); H01L 23/4822 (2013.01); H01L 23/53252 (2013.01); H01L 24/72 (2013.01);
Abstract

A release layer is formed on a surface of an integrated circuit wafer. The surface is passivated and includes metal contact materials. A stress-engineered film having an intrinsic stress profile is deposited over the release layer. The stress-engineered film is patterned and the release layer is undercut etched so that a released portion of the patterned stress-engineered film is released from the surface while leaving an anchor portion fixed to the surface. The intrinsic stress profile in the stress-engineered film biases the released portion away from the surface. The released portion is placed entirely within an area defined by the metal contact material.


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