The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 06, 2022

Filed:

Nov. 16, 2020
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Steven Verhaverbeke, San Francisco, CA (US);

Han-Wen Chen, Cupertino, CA (US);

Giback Park, San Jose, CA (US);

Chintan Buch, Santa Clara, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/552 (2006.01); H01L 23/538 (2006.01); H01L 23/532 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 23/552 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01); H01L 23/53228 (2013.01); H01L 25/0657 (2013.01);
Abstract

The present disclosure relates to thin-form-factor semiconductor packages with integrated electromagnetic interference ('EMI') shields and methods for forming the same. The packages described herein may be utilized to form high-density semiconductor devices. In certain embodiments, a silicon substrate is laser ablated to include one or more cavities and a plurality of vias surrounding the cavities. One or more semiconductor dies may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. A plurality of conductive interconnections are formed within the vias and may have contact points redistributed to desired surfaces of the die-embedded substrate assembly. Thereafter, an EMI shield is plated onto a surface of the die-embedded substrate assembly and connected to ground by at least one of the one or more conductive interconnections. The die-embedded substrate assembly may then be singulated and/or integrated with another semiconductor device.


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