The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 06, 2022

Filed:

Aug. 26, 2020
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Prakash Narayanan, Bengaluru, IN;

Nikita Naresh, Bengaluru, IN;

Prathyusha Teja Inuganti, Bengaluru, IN;

Rakesh Channabasappa Yaraduyathinahalli, Bengaluru, IN;

Aravinda Acharya, Bengaluru, IN;

Jasbir Singh, Bengaluru, IN;

Naveen Ambalametil Narayanan, Bengaluru, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/38 (2006.01); G11C 17/00 (2006.01); G11C 29/00 (2006.01); G11C 11/00 (2006.01); G11C 29/10 (2006.01); G11C 29/12 (2006.01); G11C 29/04 (2006.01); G11C 29/08 (2006.01); G11C 14/00 (2006.01); G06F 12/06 (2006.01); G06F 9/4401 (2018.01);
U.S. Cl.
CPC ...
G11C 29/38 (2013.01); G06F 12/0638 (2013.01); G11C 11/005 (2013.01); G11C 14/0054 (2013.01); G11C 17/00 (2013.01); G11C 29/04 (2013.01); G11C 29/08 (2013.01); G11C 29/10 (2013.01); G11C 29/12 (2013.01); G11C 29/822 (2013.01); G06F 9/4401 (2013.01); G11C 2029/0407 (2013.01);
Abstract

A system includes a volatile storage device, a read-only memory (ROM), a memory built-in self-test (BIST) controller and a central processing unit (CPU). The CPU, upon occurrence of a reset event, executes a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device. The CPU also executes a second instruction from the ROM to change a program counter. The CPU further executes the plurality of instructions from the volatile storage device using the program counter. The CPU, when executing the plurality of instructions from the volatile storage device, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM.


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