The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 06, 2022

Filed:

Nov. 27, 2019
Applicant:

Rockwell Collins, Inc., Cedar Rapids, IA (US);

Inventors:

Carl J. Henning, Cedar Rapids, IA (US);

David J. Radack, Robins, IA (US);

Assignee:

Rockwell Collins, Inc., Cedar Rapids, IA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 12/0891 (2016.01); G06F 9/50 (2006.01); G06F 12/0817 (2016.01); G06F 9/48 (2006.01); G06F 9/30 (2018.01); G06F 30/30 (2020.01); G06F 12/1081 (2016.01); G06F 12/0815 (2016.01); G06F 13/28 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0891 (2013.01); G06F 9/30098 (2013.01); G06F 9/3891 (2013.01); G06F 9/4843 (2013.01); G06F 9/5011 (2013.01); G06F 12/0815 (2013.01); G06F 12/0828 (2013.01); G06F 12/1081 (2013.01); G06F 13/28 (2013.01); G06F 30/30 (2020.01); G06F 2212/303 (2013.01);
Abstract

A multicore processing environment (MCPE) is disclosed. In embodiments, the MCPE includes multiple processing cores hosting multiple user applications configured for simultaneous execution. The cores and user applications share system resources including main memory and input/output (I/O) domains, each I/O domain including multiple I/O devices capable of requesting inbound access to main memory through an I/O memory management unit (IOMMU). For example, the IOMMU cache associates unique cache tags to each I/O device based on device identifiers or settings determined by the system registers, caching the configuration data for each I/O device under the appropriate cache tag. When each I/O device requests main memory access, the IOMMU cache refers to the appropriate configuration data under the corresponding unique cache tag. This prevents contention in the IOMMU cache caused by one device evicting the cache entry of another, minimizing interference channels by reducing the need for main memory access.


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