Compute-adaptive clock management for machine learning accelerators

Abstract

A system for clock management in an m columns×n rows array-based accelerators. Each row of the array may include a clock domain that clocks runtime clock cycles for the m processing elements. The clock domain includes a data detection and timing control circuit which is coupled to a common clock phase bus which provides a local clock source in multiple selectable phases, wherein the data detection and timing control circuit is configured to select a clock phase to clock a next clock cycle for a next concurrent data processing by the m processing elements. Each of m processing elements is coupled to access data from a first memory and a second memory and to generate respective outputs from each of the m processing elements to a corresponding m processing element of a same column in a subsequent neighboring row for the next processing in the next clock cycle.