The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 06, 2022

Filed:

Aug. 22, 2018
Applicant:

Commsolid Gmbh, Dresden, DE;

Inventor:

Uwe Porst, Dresden, DE;

Assignee:

COMMSOLID GMBH, Dresden, DE;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3177 (2006.01); G01R 31/3185 (2006.01); G01R 31/317 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3177 (2013.01); G01R 31/31705 (2013.01); G01R 31/31721 (2013.01); G01R 31/31724 (2013.01); G01R 31/318533 (2013.01); G01R 31/318536 (2013.01); G01R 31/318555 (2013.01); G01R 31/318597 (2013.01);
Abstract

The invention discloses an extended joint test action group based controller and a method for functional debugging using the extended joint test action group based controller. The object of the invention to lower the power dissipation (dynamic and leakage) but providing the same functionality of the testing and debugging procedures at the same time will be solved by an extended joint test action group (JTAG) controller for testing flip-flops of a register of an integrated circuit (IC) using a design for testing scan infrastructure on the IC which comprises at least one scan chain, wherein an external debugger is connected to the design for testing scan infrastructure via the JTAG controller which is extended by a debug controller, whereas a feedback loop is formed from an output of the scan chain to an input multiplexer of the scan chain which is activated according to the extended JTAG controller.


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