The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2022

Filed:

Jan. 22, 2021
Applicant:

Sunrise Memory Corporation, Fremont, CA (US);

Inventors:

Sayeef Salahuddin, Walnut Creek, CA (US);

George Samachisa, Atherton, CA (US);

Wu-Yi Henry Chien, San Jose, CA (US);

Eli Harari, Saratoga, CA (US);

Assignee:

SUNRISE MEMORY CORPORATION, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8239 (2006.01); H01L 29/792 (2006.01); H01L 27/11568 (2017.01); H01L 29/51 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/792 (2013.01); H01L 27/11568 (2013.01); H01L 29/4234 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01);
Abstract

A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer is has a value between −1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.


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