The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 29, 2022
Filed:
Dec. 10, 2020
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Inventors:
Assignee:
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3128 (2013.01); H01L 21/486 (2013.01); H01L 21/4853 (2013.01); H01L 21/565 (2013.01); H01L 21/78 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 25/0657 (2013.01); H01L 2224/16227 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06586 (2013.01);
Abstract
Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, and a molding layer. The semiconductor chip includes a circuit region and an edge region around the circuit region. The molding layer covers a sidewall of the semiconductor chip. The semiconductor chip includes a reforming layer on the edge region. A top surface of the reforming layer is coplanar with a top surface of the molding layer.