The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2022

Filed:

Jun. 30, 2021
Applicant:

Montage Lz Technologies (Chengdu) Co., Ltd., Sichuang, CN;

Inventors:

Huimin Mao, Chengdu, CN;

Shunlin Li, Chengdu, CN;

Chengqiang Liu, Chengdu, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/3308 (2020.01); G06F 30/20 (2020.01); G06F 30/367 (2020.01); G06F 11/00 (2006.01); G01R 31/28 (2006.01); G06F 115/02 (2020.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/3308 (2020.01); G01R 31/28 (2013.01); G06F 11/00 (2013.01); G06F 30/20 (2020.01); G06F 30/367 (2020.01); G06F 2115/02 (2020.01);
Abstract

The present application discloses a verification platform for a system on chip and a verification method thereof, the method comprises: constructing a simulation verification environment for the system on chip; creating a bus function model unit, and binding the bus function model unit to the same interface at which a central processing unit being connected to the bus; creating an Universal Verification Methodology test instance, and performing the Universal Verification Methodology test instance by the bus function model unit to implement the system on chip test; creating a plurality of software test instances; and compiling the software test instances, and performing the compiled software test instances by the central processing unit to implement the system on chip test.


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