Circuit for neural network convolutional calculation of variable feature and kernel sizes

Abstract

A circuit for performing parallel convolutional computation for features and kernels of variable sizes may receive inputs of an m×n matrix of feature data, an m×n matrix of convolution data, and a (2m−1)×(2n−1) matrix of kernel data. A feature manager of the circuit may hold m rows of n data buffers storing the input feature data and rotating values between rows during one restricted convolution calculation. A kernel manager of the circuit may hold a (2m−1)×(2n−1) matrix of data buffers storing the input kernel data in the buffers and cyclically rotating values in upwards, downwards, leftwards and rightwards directions for different restricted convolution calculations. A row convolution engine of the circuit may hold m row convolution processors, each storing and updating input convolution data by multiplication-and-accumulation (MAC) operations on its input feature and kernel data rows. The circuit produces accumulated convolutional data.