The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 29, 2022
Filed:
Mar. 25, 2021
Western Digital Technologies, Inc., San Jose, CA (US);
Kiran Kumar Gunnam, Santa Clara, CA (US);
Western Digital Technologies, Inc., San Jose, CA (US);
Abstract
A method, circuit, and system for managing wear levelling in non-volatile memory. First, an original physical block address (PBA) for a logical block address (LBA) of a write operation may be received. The original PBA is one of a set of PBAs for data blocks of a non-volatile memory array. Each of these PBAs may be uniquely mapped to a particular LBA using a multistage interconnection network (MIN). A swap PBA may next be determined for the LBA. The swap PBA may be selected from the set of PBAs uniquely mapped using the MIN. Then, the MIN may be configured to map the LBA to the swap PBA. Finally, data of a first data block stored at the original PBA may be swapped with data of a second data block stored at the swap PBA.