The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2022

Filed:

Apr. 29, 2021
Applicant:

Huawei Technologies Co., Ltd., Guangdong, CN;

Inventors:

Xiaofeng Zhang, Kista, SE;

Dan Liang, Shanghai, CN;

Zheng Cui, Dongguan, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01P 1/20 (2006.01); H01P 1/205 (2006.01); H01P 1/208 (2006.01); H01P 7/10 (2006.01); H01P 7/04 (2006.01);
U.S. Cl.
CPC ...
H01P 1/2056 (2013.01); H01P 1/2002 (2013.01); H01P 1/2084 (2013.01); H01P 7/04 (2013.01); H01P 7/10 (2013.01);
Abstract

This application provides an example dielectric filter and an example communications device. The dielectric filter includes a dielectric block. At least two resonant through holes that are parallel to each other are provided in the dielectric block. The resonant through hole is a stepped hole. The stepped hole includes a large stepped hole and a small stepped hole that are arranged coaxially and that are in communication. The small stepped hole passes through a first surface of the dielectric block. The large stepped hole passes through a second surface of the dielectric block. A stepped surface is formed between the large stepped hole and the small stepped hole. The surfaces of the dielectric block are covered with conductor layers. The conductor layers cover the surfaces of the dielectric block and inner walls of the large stepped hole and the small stepped hole. A conductor layer of the inner wall of the large stepped hole is short-circuited with a conductor layer of the second surface. A conductor layer of the inner wall of the small stepped hole is short-circuited with a conductor layer of the first surface. A loop gap that does not cover the conductor layers is provided on the stepped surface. The loop gap is arranged around the small stepped hole.


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