The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2022

Filed:

Dec. 02, 2020
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Takeki Ninomiya, Yokkaichi, JP;

Teruo Okina, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2006.01); H01L 23/00 (2006.01); H01L 27/11582 (2017.01); H01L 27/11565 (2017.01); H01L 27/1157 (2017.01); H01L 27/11573 (2017.01); H01L 27/11519 (2017.01); H01L 27/11524 (2017.01); H01L 27/11529 (2017.01); H01L 27/11556 (2017.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 23/481 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 27/1157 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11529 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11573 (2013.01); H01L 27/11582 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1438 (2013.01);
Abstract

A memory die includes an alternating stack of insulating layers and electrically conductive layers, memory stack structures extending through the alternating stack, and each of the memory stack structures includes a respective vertical semiconductor channel and a respective memory film, drain regions located at a first end of a respective one of the vertical semiconductor channels, and a source layer having a first surface and a second surface. The first surface is located at a second end of each of the vertical semiconductor channels, and a semiconductor wafer is not located over the second surface of the source layer.


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