The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2022

Filed:

Sep. 18, 2020
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Min Hwan Moon, Icheon-si, KR;

Se Joong Kim, Icheon-si, KR;

Assignee:

SK HYNIX INC., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G11C 29/42 (2006.01); G11C 29/44 (2006.01); G11C 29/14 (2006.01); G11C 29/12 (2006.01); G11C 16/08 (2006.01); G11C 29/52 (2006.01);
U.S. Cl.
CPC ...
G11C 29/42 (2013.01); G11C 29/14 (2013.01); G11C 29/44 (2013.01); G11C 16/08 (2013.01); G11C 29/52 (2013.01); G11C 2029/1202 (2013.01);
Abstract

A data storage device including a memory device and a memory controller is disclosed. The memory controller including a super block includes a parity controller in communication with a memory device including a plurality of pages and configured to generate a first parity using data to be written to a first group of pages among the plurality of pages, and generate a second parity using data to be written to a second group of pages among the plurality of pages, a write operation controller configured to control the memory device to store the first parity and the second parity, and an error correction circuitry coupled to apply the first parity and the second parity to correct at least one of the plurality of pages arranged to belong to the first group of pages and the second group of pages.


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