The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2022

Filed:

Oct. 05, 2021
Applicant:

Realtek Semiconductor Corporation, Hsinchu, TW;

Inventors:

Sheng-Lin Lin, Hsinchu, TW;

Shih-Chieh Lin, Hsinchu, TW;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/02 (2006.01); G01R 31/3185 (2006.01); G11C 29/30 (2006.01); G11C 29/14 (2006.01); G11C 29/32 (2006.01); G11C 29/12 (2006.01); G11C 29/56 (2006.01);
U.S. Cl.
CPC ...
G11C 29/025 (2013.01); G01R 31/318541 (2013.01); G11C 29/1201 (2013.01); G11C 29/14 (2013.01); G11C 29/30 (2013.01); G11C 29/32 (2013.01); G11C 29/56008 (2013.01); G11C 2029/3202 (2013.01);
Abstract

The present application provides a circuit and an associated chip. The circuit is coupled to a memory. The circuit includes: a first scan flip-flop (FF), being a previous-stage scan FF of an input terminal of the memory and having an output terminal coupled to an input terminal of the memory; and a second scan FF, being a next-stage scan FF of an output terminal of the memory and having an input terminal coupled to an output terminal of the memory; wherein a scan mode of the circuit has a load phase and a capture phase, during the capture phase, data output from the output terminal of the first scan FF loops back to a data input terminal of the first scan FF via a first loop, and the first loop is free from passing through the second scan FF.


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