The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2022

Filed:

Dec. 12, 2017
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Matthias Lothar Boettcher, Cambridge, GB;

Mbou Eyole, Soham, GB;

Nathanael Premillieu, Antibus, FR;

Assignee:

Arm Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/16 (2006.01); G06F 9/30 (2018.01); G06F 11/07 (2006.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 11/1637 (2013.01); G06F 9/30036 (2013.01); G06F 9/30043 (2013.01); G06F 9/30145 (2013.01); G06F 9/3836 (2013.01); G06F 9/3889 (2013.01); G06F 11/0721 (2013.01); G06F 11/0751 (2013.01); G06F 11/1683 (2013.01); G06F 11/1679 (2013.01); G06F 2201/845 (2013.01);
Abstract

A data processing apparatus () has scalar processing circuitry (-) and vector processing circuitry (). When executing main scalar processing on the scalar processing circuitry (-), or main vector processing using a subset of said plurality of lanes on the vector processing circuitry (), checker processing is executed using at least one lane of the plurality of lanes on the vector processing circuitry (), the checker processing comprising operations corresponding to at least part of the main scalar/vector processing. Errors can then be detected based on a comparison of an outcome of the main processing and an outcome of the checker processing. This provides a technique for achieving functional safety in a high end processor with better performance and reduced hardware cost compared to a dual/triple core lockstep approach.


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