The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2022

Filed:

Dec. 10, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Heejin Kim, Suwon-si, KR;

Hyunjun Yoon, Changwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/07 (2006.01); G06F 12/0882 (2016.01); G11C 7/10 (2006.01); G11C 11/4093 (2006.01); G11C 11/4074 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 11/0778 (2013.01); G06F 11/0757 (2013.01); G06F 12/0882 (2013.01); G06F 13/1673 (2013.01); G11C 7/1039 (2013.01); G11C 7/1087 (2013.01); G11C 11/4074 (2013.01); G11C 11/4093 (2013.01);
Abstract

A non-volatile memory device, a method of operating the non-volatile memory device, and a memory system including the non-volatile memory device are provided. A non-volatile memory device includes a memory cell array including a plurality of memory cells configured to be each programmed to one state of a plurality of states, a page buffer circuit including a plurality of page buffers configured to each store received data as state data indicating a target state of a corresponding one of the plurality of memory cells, the page buffer circuit being configured to perform a state data reordering operation of changing a first state data order into a second state data order during performance of a program operation on selected memory cells of the plurality of memory cells, and a reordering control circuit configured to control the page buffer circuit to perform the state data reordering operation simultaneously with the program operation.


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