The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2022

Filed:

Mar. 26, 2021
Applicant:

Quadric.io, Inc., Burlingame, CA (US);

Inventors:

Nigel Drego, Burlingame, CA (US);

Aman Sikka, Burlingame, CA (US);

Mrinalini Ravichandran, Burlingame, CA (US);

Robert Daniel Firu, Burlingame, CA (US);

Veerbhan Kheterpal, Burlingame, CA (US);

Assignee:

quadric.io, Inc., Burlingame, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 15/80 (2006.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3897 (2013.01); G06F 9/5061 (2013.01); G06F 9/5066 (2013.01); G06F 9/5072 (2013.01); G06F 9/5077 (2013.01); G06F 15/80 (2013.01); G06F 15/8023 (2013.01); G06F 2212/152 (2013.01);
Abstract

Systems and methods for virtually partitioning an integrated circuit may include identifying dimensional attributes of a target input dataset and selecting a data partitioning scheme from a plurality of distinct data partitioning schemes for the target input dataset based on the dimensional attributes of the target dataset and architectural attributes of an integrated circuit. The methods described herein may also include disintegrating the target dataset into a plurality of distinct subsets of data based on the selected data partitioning scheme and identifying a virtual processing core partitioning scheme from a plurality of distinct processing core partitioning schemes for an architecture of the integrated circuit based on the disintegration of the target input dataset. Additionally, the architecture of the integrated circuit may be virtually partitioned into a plurality of distinct partitions of processing cores and each of the plurality of distinct subsets of data may be mapped to one of the plurality of distinct partitions of processing cores.


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