The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 22, 2022
Filed:
Nov. 27, 2019
Cambricon (Xi'an) Semiconductor Co., Ltd., Xi'an, CN;
Tianshi Chen, Pudong New Area, CN;
Shengyuan Zhou, Pudong New Area, CN;
Zidong Du, Pudong New Area, CN;
Qi Guo, Pudong New Area, CN;
CAMBRICON (XI'AN) SEMICONDUCTOR CO., LTD., Xi'an, CN;
Abstract
The present disclosure relates to a fused vector multiplier for computing an inner product between vectors, where vectors to be computed are a multiplier number vector {right arrow over (A)}{AN . . . A2A1A0} and a multiplicand number {right arrow over (B)} {BN . . . B2B1B0}, {right arrow over (A)} and {right arrow over (B)} have the same dimension which is N+1. The multiplier includes: N+1 multiplication sub-units configured to perform multiplication on each dimension of a vector respectively, and take lower n bits of the multiplier number vector for multiplication each time, where the n bits are removed from the binary number of each dimension of the multiplier number vector after the n bits are taken, and n is larger than 1 and less than N+1; an adder tree configured to perform addition on results of N+1 multiplication sub-units obtained from a same operation each time; and a result register configured to hold a result of every addition performed by the adder tree and send the result to the adder tree for next computation.