The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 22, 2022
Filed:
Oct. 05, 2020
Applicant:
Futurewei Technologies, Inc., Plano, TX (US);
Inventor:
Yiren Huang, San Jose, CA (US);
Assignee:
Futurewei Technologies, Inc., Plano, TX (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 11/10 (2006.01); G11C 29/00 (2006.01); G11C 29/52 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0619 (2013.01); G06F 3/064 (2013.01); G06F 3/0629 (2013.01); G06F 3/0638 (2013.01); G06F 3/0688 (2013.01); G06F 3/0689 (2013.01); G06F 11/106 (2013.01); G06F 11/1068 (2013.01); G06F 12/0246 (2013.01); G11C 29/52 (2013.01); G11C 29/82 (2013.01); G06F 11/108 (2013.01); G06F 2212/7208 (2013.01); Y02D 10/00 (2018.01);
Abstract
A solid state drive (SSD) employing a redundant array of independent disks (RAID) scheme includes a flash memory chip, erasable blocks in the flash memory chip, and a flash controller. The erasable blocks are configured to store flash memory pages. The flash controller is operably coupled to the flash memory chip. The flash controller is also configured to organize certain of the flash memory pages into a RAID line group and to write RAID line group membership information to each of the flash memory pages in the RAID line group.