The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2022

Filed:

Nov. 15, 2021
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Ji Hwan Park, Gyeonggi-do, KR;

Jun Il Moon, Gyeonggi-do, KR;

Byung Kuk Yoon, Gyeonggi-do, KR;

Myeong Jae Park, Gyeonggi-do, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/07 (2006.01); H04L 7/00 (2006.01); H04L 7/033 (2006.01); H03L 7/08 (2006.01); H03L 7/081 (2006.01); H03L 7/091 (2006.01); H03K 5/135 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0025 (2013.01); H03K 5/135 (2013.01); H03L 7/07 (2013.01); H03L 7/0807 (2013.01); H03L 7/0814 (2013.01); H03L 7/091 (2013.01); H04L 7/0337 (2013.01); H03K 2005/00052 (2013.01);
Abstract

A clock generator circuit includes: first to Nnodes, where N is an even number equal to or greater than 2; and a parallel-to-serial conversion circuit suitable for parallel-to-serial converting signals of the first to Nnodes to output a clock through an output node, wherein, in an activation section of the clock, the signals of even-numbered nodes among the first to Nnodes have a first level, and the signals of odd-numbered nodes among the first to Nnodes have a second level which is different from the first level, and wherein, in a deactivation section of the clock, the signals of the first to Nnodes have the same level.


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