The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2022

Filed:

Jul. 25, 2018
Applicant:

No. 24 Research Institute of China Electronics Technology Group Corporation, Chongqing, CN;

Inventors:

Xiaofeng Shen, Chongqing, CN;

Xingfa Huang, Chongqing, CN;

Liang Li, Chongqing, CN;

Xi Chen, Chongqing, CN;

Mingyuan Xu, Chongqing, CN;

Jian'an Wang, Chongqing, CN;

Dongbing Fu, Chongqing, CN;

Guangbing Chen, Chongqing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/45 (2006.01); H03F 3/68 (2006.01); H03K 3/012 (2006.01); H03K 3/013 (2006.01);
U.S. Cl.
CPC ...
H03F 3/45269 (2013.01); H03F 3/45636 (2013.01); H03F 3/68 (2013.01); H03K 3/012 (2013.01); H03K 3/013 (2013.01);
Abstract

A clock driver circuit, including: an input stage, a double-ended to single-ended conversion stage and a driver output stage connected in sequence. The input stage includes two mutually loaded differential amplifiers and a common mode negative feedback loop. The differential amplifiers are connected to a differential clock signal for amplification to generate a common mode voltage. The common mode feedback circuit is connected to an output end of the differential amplifiers to stabilize the output amplitude of the common mode voltage. The double-ended to single-ended conversion stage converts a differential sine clock signal output by the double-ended common mode voltage into a single-ended square wave clock signal. The driver output stage includes a multi-stage cascaded push-pull phase inverter to improve the drive capability of the square wave clock signal.


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