The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2022

Filed:

Nov. 08, 2019
Applicant:

Sunpower Corporation, San Jose, CA (US);

Inventors:

Seung Bum Rim, Palo Alto, CA (US);

David D. Smith, Campbell, CA (US);

Taiqing Qiu, Los Gatos, CA (US);

Staffan Westerberg, Sunnyvale, CA (US);

Kieran Mark Tracy, San Jose, CA (US);

Venkatasubramani Balu, Santa Clara, CA (US);

Assignee:

SunPower Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/0224 (2006.01); H01L 31/068 (2012.01); H01L 31/20 (2006.01); H01L 31/0216 (2014.01); H01L 31/0745 (2012.01); H01L 31/0747 (2012.01); H01L 31/18 (2006.01); H01L 31/0236 (2006.01); H01L 31/0368 (2006.01);
U.S. Cl.
CPC ...
H01L 31/022441 (2013.01); H01L 31/02167 (2013.01); H01L 31/02168 (2013.01); H01L 31/02363 (2013.01); H01L 31/03682 (2013.01); H01L 31/068 (2013.01); H01L 31/0682 (2013.01); H01L 31/0745 (2013.01); H01L 31/0747 (2013.01); H01L 31/182 (2013.01); H01L 31/1804 (2013.01); H01L 31/202 (2013.01); H01L 31/208 (2013.01); Y02E 10/547 (2013.01); Y02P 70/50 (2015.11);
Abstract

Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region.


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