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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11502171 B1

PDFFull Text
Date of Patent:
Nov. 15, 2022

Filed:

Dec. 28, 2020

Leakage-free implantation-free etsoi transistors

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Joel P. De Souza, Putnam Valley, NY (US);

Keith E. Fogel, Hopewell Junction, NY (US);

JeeHwan Kim, Los Angeles, CA (US);

Devendra K. Sadana, Pleasantville, NY (US);

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);

Attorneys:

Tutunjian & Bitetto, P.C.

Samuel Waldbaum

Primary Examiner:

Mary A Wilczewski

Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/8234 (2006.01); H01L 29/267 (2006.01); H01L 29/786 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 29/26 (2006.01); H01L 21/425 (2006.01); H01L 21/445 (2006.01); H01L 21/768 (2006.01); H01L 27/12 (2006.01); H01L 29/417 (2006.01); H01L 29/45 (2006.01); H01L 29/06 (2006.01); H01L 21/84 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0847 (2013.01); H01L 21/02488 (2013.01); H01L 21/02554 (2013.01); H01L 21/02565 (2013.01); H01L 21/02576 (2013.01); H01L 21/02587 (2013.01); H01L 21/425 (2013.01); H01L 21/445 (2013.01); H01L 21/76895 (2013.01); H01L 27/127 (2013.01); H01L 27/1225 (2013.01); H01L 29/263 (2013.01); H01L 29/267 (2013.01); H01L 29/41733 (2013.01); H01L 29/45 (2013.01); H01L 29/66742 (2013.01); H01L 29/66772 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78603 (2013.01); H01L 29/78618 (2013.01); H01L 29/78654 (2013.01); H01L 29/78681 (2013.01); H01L 29/78684 (2013.01); H01L 29/78693 (2013.01); H01L 29/78696 (2013.01); H01L 21/02521 (2013.01); H01L 21/02551 (2013.01); H01L 21/84 (2013.01); H01L 29/0638 (2013.01);
Abstract

A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.

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